Semiconductor integrated circuits have progressively reduced their feature line widths into the deep sub-micron region. Recent developments in certain memory cell technologies have resulted in word lines and bit lines having an extremely small pitch. For example, certain passive element memory cell arrays may be fabricated having word lines approaching the minimum feature size and minimum feature spacing for the particular word line interconnect layer. Such passive element memory cell arrays also have bit lines approaching the minimum feature with and minimum feature spacing for the particular bit line interconnect layer. Additionally, three-dimensional memory arrays having more than one plane of memory cells have been fabricated containing so-called 4F2 memory cells on each memory plane.